1 nov-05-2004 n-channel logic level enhancement mode field effect transistor P1402CDG to-252 (dpak) lead-free niko-sem absolute maximum ratings (t c = 25 c unless otherwise noted) parameters/test conditions symbol limits units gate-source voltage v gs 12 v t c = 25 c 45 continuous drain current t c = 100 c i d 30 pulsed drain current 1 i dm 140 a t c = 25 c 48 power dissipation t c = 100 c p d 20 w operating junction & storage temperature range t j , t stg -55 to 150 lead temperature ( 1 / 16 ? from case for 10 sec.) t l 275 c thermal resistance ratings thermal resistance symbol typical maximum units junction-to-case r jc 2.6 junction-to-ambient r ja 110 c / w 1 pulse width limited by maximum junction temperature. 2 duty cycle 1 electrical characteristics (t c = 25 c, unless otherwise noted) limits parameter symbol test conditions min typ max unit static drain-source breakdown voltage v (br)dss v gs = 0v, i d = 250 a 20 gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.45 0.75 1.25 v gate-body leakage i gss v ds = 0v, v gs = 12v 100 na v ds = 16v, v gs = 0v 1 zero gate voltage drain current i dss v ds = 13.2v, v gs = 0v, t j = 125 c 10 a on-state drain current 1 i d(on) v ds = 5v, v gs = 4.5v 45 a v gs = 2.5v, i d = 9a 18 26 drain-source on-state resistance 1 r ds(on) v gs = 5v, i d = 18a 11 14 m ? forward transconductance 1 g fs v ds = 10v, i d = 18a 26 s 1. gate 2. drain 3. source product summary v (br)dss r ds(on) i d 20 14m ? 45a g d s
2 nov-05-2004 n-channel logic level enhancement mode field effect transistor P1402CDG to-252 (dpak) lead-free niko-sem dynamic input capacitance c iss 500 output capacitance c oss 310 reverse transfer capacitance c rss v gs = 0v, v ds = 15v, f = 1mhz 125 pf total gate charge 2 q g 17 gate-source charge 2 q gs 1.5 gate-drain charge 2 q gd v ds = 0.5v (br)dss , v gs = 5v, i d = 18a 10.5 nc turn-on delay time 2 t d(on) 7.5 rise time 2 t r v ds = 10v, 83 turn-off delay time 2 t d(off) i d ? 18a, v gs = 5v, r gs = 3.3 ? 18 fall time 2 t f 23 ns source-drain diode ratin gs and characteristics (t c = 25 c) continuous current i s 45 pulsed current 3 i sm 140 a forward voltage 1 v sd i f = i s , v gs = 0v 1.3 v reverse recovery time t rr 37 ns peak reverse recovery current i rm(rec) i f = i s , dl f /dt = 100a / s 200 a reverse recovery charge q rr 0.043 c 1 pulse test : pulse width 300 sec, duty cycle 2 . 2 independent of operating temperature. 3 pulse width limited by maximum junction temperature. remark: the product marked with ?P1402CDG?, date code or lot # orders for parts with lead-free plating can be placed using the pxxxxxxg parts name.
3 nov-05-2004 n-channel logic level enhancement mode field effect transistor P1402CDG to-252 (dpak) lead-free niko-sem body diode forward voltage variation with source current and temperature is - reverse drain current(a) 0.0001 0 0.001 0.01 0.4 0.2 0.6 v = 0v 1 0.1 10 60 t = 125 c 25 c gs 1.0 0.8 1.2 -55 c 1.4 v - body diode forward voltage(v) sd
4 nov-05-2004 n-channel logic level enhancement mode field effect transistor P1402CDG to-252 (dpak) lead-free niko-sem
5 nov-05-2004 n-channel logic level enhancement mode field effect transistor P1402CDG to-252 (dpak) lead-free niko-sem to-252 (dpak) mechanical data mm mm dimension min. typ. max. dimension min. typ. max. a 9.35 10.4 h 0.89 2.03 b 2.2 2.4 i 6.35 6.80 c 0.45 0.6 j 5.2 5.5 d 0.89 1.5 k 0.6 1 e 0.45 0.69 l 0.5 0.9 f 0.03 0.23 m 3.96 4.57 5.18 g 5.2 6.2 n g a h j i b c m l k d e f 13 2
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